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Espressif Systems /ESP32-S2 /SENS /SAR_COCPU_STATE

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Interpret as SAR_COCPU_STATE

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (COCPU_DBG_TRIGGER)COCPU_DBG_TRIGGER 0 (COCPU_CLK_EN)COCPU_CLK_EN 0 (COCPU_RESET_N)COCPU_RESET_N 0 (COCPU_EOI)COCPU_EOI 0 (COCPU_TRAP)COCPU_TRAP 0 (COCPU_EBREAK)COCPU_EBREAK

Description

ULP-RISCV status

Fields

COCPU_DBG_TRIGGER

Trigger ULP-RISCV debug registers
COCPU_CLK_EN

Check ULP-RISCV whether clk on
COCPU_RESET_N

Check ULP-RISCV whether in reset state
COCPU_EOI

Check ULP-RISCV whether in interrupt state
COCPU_TRAP

Check ULP-RISCV whether in trap state
COCPU_EBREAK

Check ULP-RISCV whether in ebreak

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/espressif/svd